- 課程概述
- 老師簡介
- 課程大綱
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課程背景高速PCB設(shè)計的潮流已經(jīng)滾滾而來，如何預(yù)防PCB板上出現(xiàn)的信號反射、串?dāng)_、電源/地平面干擾、時序匹配以及電磁兼容性等一系列新問題好象突然間擋在了您的面前。如何應(yīng)對新的設(shè)計挑戰(zhàn)？Cadence培訓(xùn)高級班將首先讓您了解這些問題產(chǎn)生的機理，并掌握其解決方法；然后講解并上機練習(xí)Cadence的高速 PCB設(shè)計與仿真工具SPECCTRAQuest的使用。使您在硬件設(shè)計過程中，能夠達到“設(shè)計即正確”的目的。
教材◆ 《華清遠見Cadence PCB設(shè)計高級班培訓(xùn)講義》
新優(yōu)惠◆團體報名優(yōu)惠措施：兩人95折優(yōu)惠，三人或三人以上9折優(yōu)惠
◆同時報選《Cadence PCB設(shè)計初級班》，即享受500元優(yōu)惠！實驗環(huán)境為了保證培訓(xùn)效果，增加互動環(huán)節(jié)，我們堅持小班授課，每期報名人數(shù)限15人，多余人員安排到下一期進行。
學(xué)時費用◆課時：共3天，每天6學(xué)時，總計18學(xué)時
◆費用（含教材費）：3000元
◆培訓(xùn)證書（可選）：培訓(xùn)合格學(xué)員可獲工業(yè)和信息化部《信息技術(shù)應(yīng)用技能Cadence設(shè)計工程師認證證書》（認證費500元）
◆外地學(xué)員：代理安排食宿（需提前預(yù)定）質(zhì)量保證1、培訓(xùn)過程中，如有部分內(nèi)容理解不透或消化不好，可免費在下期培訓(xùn)班中重聽；
2、培訓(xùn)結(jié)束后免費提供一個月的技術(shù)支持，充分保證培訓(xùn)后出效果；
3、培訓(xùn)合格學(xué)員可享受免費推薦就業(yè)機會。 -
葛老師
嵌入式頂尖級導(dǎo)師 華清遠見高級講師，長期從事教學(xué)與科研工作，主要研究方向包括網(wǎng)絡(luò)通信、視頻/圖像處理、數(shù)據(jù)庫等。具有15年的硬件設(shè)計經(jīng)驗，尤其是近6年來一直從事相關(guān)領(lǐng)域的高速DSP系統(tǒng)硬、軟件和FPGA開發(fā)經(jīng)驗數(shù)字電路設(shè)計工作，具有非常豐富的高速PCB設(shè)計經(jīng)驗。精通TI公司的C6000、ADI公司的TigerSHarc-201等系列高速DSP，成功開發(fā)了多個高速DSP和FPGA結(jié)合的高難度項目，尤其擅長多處理器系統(tǒng)的開發(fā)，熟悉多種圖像/視頻壓縮算法，在計算機學(xué)報等刊物上發(fā)表論文20余篇。葛老師授課視頻 -
第一天
1、高速PCB設(shè)計中的理論基礎(chǔ)
傳輸線理論、信號完整性（反射、串?dāng)_、過沖、地彈、振鈴等）、電磁兼容性和時序匹配等等。2、SPECCTRAQuest設(shè)計流程
2.1 Pre-Placement
2.2 Board Setup Requirements for Extracting and Applying Topologies
2.3 Database Setup Advisor
—Cross-Section
—DC Nets
—DC Voltages
—Device Setup
—SI Models
—SI Audit3、拓撲結(jié)構(gòu)的抽取與仿真 Extracting and Simulating Topologies
3.1 Pre-Route Extraction Setup—Default Model Selection
3.2 Pre-Route Extraction Setup—Unrouted Interconnect
3.3 Pre-Route Template Extraction
3.4 SQ Signal Explorer Expert
3.5 Analysis Preferences
3.6 SigWave
3.7 Delay Measurements第二天4、確定和施加約束 Determining and Adding ConstraintsSolution
4.1 Solution SpaceAnalysis: Step 1 to 6
4.2 Parametric Sweeps
4.3 Constraints
Topology Template Constraints
Switch/Settle Constraints
Assigning the Prop Delay Constraints
Impedance Constraint
Relative Propagation Delay Constraint
Diff Pair Constraints
Max Parallel Constraint
Wiring Constraint
User-Defined Constraint
Signal Integrity Constraints
4.4 Usage of Constraints Defined in Topology Template5、模板應(yīng)用和基于約束的布局
Template Applications and Constraint-Driven Placement
5.1 Creating a Topology
5.2 Wiring the Topology
5.3 TLines and Trace Models
5.4 Coupled Traces
5.5 RLGC Matrix of Coupled Trace Models
5.6 Crosstalk Simulation in SQ Signal Explorer Expert
5.7 Simulating with Coupled-Trace Models
5.8 Sweep Simulation Results with Coupled-Trace Models
5.9 Extracting a Topology Using the Constraint Manager
5.10 Electrical Constraint Set
5.11 Applying Electrical CSet
5.12 Worksheet Analysis
5.13 Spacing and Physical Rule Sets
5.14 Electrical Rule Set第三天6、基于約束的布線 Constraint-Driven Routing
6.1 Manual Routing
6.2 Routing with the SPECCTRA Smart Route
6.3 Driving Constraints in Routing7、布線后的DRC檢查和分析 Post-Route DRC and Analysis
7.1 Post-Route Analysis
7.2 SigNoise
7.3 Reflection Simulation
7.4 Reflection Waveform Analysis
7.5 Comprehensive Simulation
7.6 Crosstalk Simulation
7.7 Crosstalk Analysis
7.8 Simultaneous Switching Noise Simulation
7.9 SSN Waveform Analysis
7.10 System-Level Analysis
7.11 A Complete Design Link
7.12 Initialize Design Link8、差分信號設(shè)計 Differential Pair Design Exploration
8.1 Types of Differential Pairs in SPECCTRAQuest
8.2 Create Differential Pair Using SPECCTRAQuest
8.3 Create Differential Pair Using Constraint Manager
8.4 Assigning Differential Pair Signal Models
8.5 Preference to Extract Unrouted Differential Pair Topology
8.6 Extracting Unrouted Differential Pair Topology
8.7 Custom Stimulus to Analyze Differential Pair Topology
8.8 Differential Pair Topology Analysis
8.9 Coupled Trace Model and Differential Pair Topology
8.10 Layout Cross-section Editor
8.11 Differential Pair Constraints
8.12 Differential Pair Constraints in the Constraint Manager
8.13 Differential Pair Analysis in the Constraint Manager
8.14 Post Route Extraction
